Semiconductor devices, for example as disclosed in Japanese Unexamined Patent Publication (Kokai) No. 2002-151644, include single semiconductor devices into which a plurality of semiconductor chips or a plurality of semiconductor devices are assembled, that is, stack semiconductor devices.
The stack semiconductor device 1 shown in FIG. 10 has a structure called a “multi-chip package” or a “die stack”. Semiconductor chips 10 are stacked on a board 12, the semiconductor chips 10 and connection electrodes 13 provided on the board 12 are connected by wire bonding, one surface of the board 12 (surface on which semiconductor chips are carried) is sealed by a sealing resin 14, and solder balls 16 are connected to the mounting surface of the board 12.
The stack semiconductor device 2 shown in FIG. 11 has a so-called “package stack” structure. A plurality of semiconductor devices 11 comprised of boards 12 on which semiconductor chips 10 are mounted by flip-chip connection are stacked. The semiconductor devices 11 are electrically connected through solder balls 18 between the boards 12.
The stack semiconductor device 1 having the multi-chip package or die stack structure shown in FIG. 10 has the advantage of enabling a plurality of semiconductor chips 10 to be compactly housed in a single stack semiconductor device 1.
However, there is the problem that product tests are conducted by using the solder balls 16 as test pads after a plurality of semiconductor chips 10 are placed on the boards 12, so if even just some of the semiconductor chips 10 are defective, the product 1 as a whole is judged defective and even the good semiconductor chips 10 end up being discarded.
This problem becomes more serious the greater the number of the semiconductor chips 10 stacked. That is, if the number of the semiconductor chips 10 stacked increases, the probability will rise of defective semiconductor chips 10 being included in the product 1, so the defect rate of the product 1 will rise and good semiconductor chips 10 wastefully discarded will increase.
To solve this problem, it is sufficient to test the individual semiconductor chips 10 to judge if they are good or defective in advance, then place them on the boards 12. However, directly testing conventional semiconductor chips 10 has been difficult due to the following reasons.
That is, testing semiconductor chips 10 requires that the electrode terminals (aluminum pads) be connected to the test apparatus, but electrode terminals are arranged at intervals of a narrow 50 to 100 μm, so it is necessary to use a special test apparatus provided with special sockets for connection with the electrode terminals. Due to this, the production costs are raised.
As opposed to this, in the case of the stack semiconductor device 2 shown in FIG. 11, the semiconductor devices 11 comprised of the semiconductor chips 10 placed on the boards 12 can be individually tested to judge if they are good or defective in advance, then a plurality of only the good semiconductor devices 11 stacked to obtain the product 2.
With this method, however, (1) the number of the boards 12 increases and the production costs increase, (2) the boards 12 are joined at the board peripheries at the outside from the regions for carrying the semiconductor chips 10, so the planar dimensions of the semiconductor devices 11 and in the end the planar dimensions of the stack semiconductor device 2 cannot be reduced, and (3) since a plurality of not only semiconductor chips 10 and boards 12 are stacked, the stack semiconductor device 2 as a whole increases in thickness.